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자료 필터
자료유형
발행연도
1996 ~ 2026
1996 2026
키워드
언어
선택된 필터
- conference
- article
- book
전체 169건 중 141번부터 150번까지의 결과를 표시합니다.
2003
Conference
Unified low power optimization algorithm by gate freezing, gate sizing and buffer insertion
- 2003-02-01
Article
Combining transistor sizing, wire sizing, and buffer insertion for low power in CMOS digital circuit design
- Lee, H ;
- Kim, J
- 2003-02
- Journal of the Korean Physical Society
- 한국물리학회
2002
Conference
Transistor sizing considering slew information to reduce glitch power in CMOS Digital circuit design
- 2002-07-01
Article
Concurrent gate re-sizing and buffer insertion to reduce glitch power in CMOS digital circuit design
- Kim, SJ ;
- Lee, HW ;
- Kim, JH
- 2002-01
- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
- Oxford University Press
2001
Article
A post-layout optimization by combining buffer insertion and transistor sizing
- Lee, S ;
- Kim, J
- 2001-10
- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
- Oxford University Press
2000