Combining transistor sizing, wire sizing, and buffer insertion for low power in CMOS digital circuit design

초록

The capacitance is the dominant factor for power dissipation in CMOS digital circuits. Transistor sizing, wire sizing, and buffer insertion are well-known optimization techniques for reducing the total capacitance of a circuit. In this paper, we present a novel algorithm that combines transistor sizing, buffer insertion, and wire sizing for power optimization. By combining three different optimization methods into one process, we can achieve more power reduction than we can by applying them independently. In addition, our algorithm adds flexibility to the optimization since there is no single technique suitable for all circuits. We compare our results to those of transistor sizing or wire sizing alone and to those of transistor sizing with wire sizing. Our experimental results verify that the proposed algorithm is very effective for power optimization.

키워드