Research Team Led by Professor Ryu Sung-ju Has Paper Accepted to Top Conference ‘ICCAD 2025’ in Semiconductor Design Automation
A paper completed by Professor Ryu Sung-ju’s research team from Sogang University’s Department of System Semiconductor Engineering and Department of Electronic Engineering has been accepted to the “International Conference on Computer-Aided Design (ICCAD) 2025,” a top conference in the field of semiconductor design automation. Since 1982, ICCAD has been recognized as a prestigious international conference driving advancements in semiconductors, VLSI (Very Large Scale Integration) design, and related technologies, and the 2025 edition will be held in Munich, Germany, from October 26 to 30.
The paper, titled “OptiRange: An Efficient ReRAM-Based PIM Accelerator with ADC Resolution Optimization”, was led by Jeon Sang-kyu (Ph.D. integrated program), with contributions from Ji Ki-san (Ph.D. integrated program), Kim Young-geon (master’s program), Park Young-jun (master’s program), and Kim Sang-yeon (Ph.D. integrated program).
As the number of parameters in AI models grows exponentially, processing-in-memory (PIM) architectures are being researched as a promising approach to address the memory bottleneck caused by data transfer. Notably, ReRAM-based (resistive memory) PIM has attracted attention for its high parallelism and energy efficiency, but the substantial energy consumption of analog-to-digital converters (ADCs), which convert analog computation results into digital signals, has remained a major obstacle.
Previous research suggested quantizing weights and adding extra hardware to reduce ADC energy consumption, but that method often resulted in decreased model accuracy and significant hardware overhead.
To address this challenge, the research team analyzed the phenomenon in PIM circuits where certain data operations consume excessively high current and developed the OptiRange architecture as a solution to this problem.
This technology preserves AI model weights while adding only minimal additional hardware to solve the problems from the conventional research. It reconstructs the conductance values stored in ReRAM cells at the software level and adjusts the dynamic ADC range to minimize unnecessary ADC steps. The technique (1) detects cell values that unnecessarily require high ADC resolution and redistributes them to neighboring cells using the Split-the-Burden (STB) algorithm, and (2) skips redundant ADC steps through the Dynamic ADC Range (DAR) technique based on the reconfigured cell values.
According to the research, OptiRange achieves up to 3 times energy savings and up to 1.4 times speed improvement compared to state-of-the-art (SOTA) models. This research is expected to contribute not only to ReRam-based PIN but reducing ADC energy consumption and latency in a wide range of PIM hardware designs.
▶ Paper title: “OptiRange: An Efficient ReRAM-Based PIM Accelerator with ADC Resolution Optimization”
▶Authors: Ji Ki-san (Second Author, Ph.D. Integrated Program), Kim Young-geon (Third Author, Master’s Program), Park Young-jun (Fourth Author, Master’s Program), Kim Sang-yeon (Fifth Author, Ph.D. Integrated Program), and Professor Ryu Sung-ju (Corresponding Author)
The paper, titled “OptiRange: An Efficient ReRAM-Based PIM Accelerator with ADC Resolution Optimization”, was led by Jeon Sang-kyu (Ph.D. integrated program), with contributions from Ji Ki-san (Ph.D. integrated program), Kim Young-geon (master’s program), Park Young-jun (master’s program), and Kim Sang-yeon (Ph.D. integrated program).
As the number of parameters in AI models grows exponentially, processing-in-memory (PIM) architectures are being researched as a promising approach to address the memory bottleneck caused by data transfer. Notably, ReRAM-based (resistive memory) PIM has attracted attention for its high parallelism and energy efficiency, but the substantial energy consumption of analog-to-digital converters (ADCs), which convert analog computation results into digital signals, has remained a major obstacle.
Previous research suggested quantizing weights and adding extra hardware to reduce ADC energy consumption, but that method often resulted in decreased model accuracy and significant hardware overhead.
To address this challenge, the research team analyzed the phenomenon in PIM circuits where certain data operations consume excessively high current and developed the OptiRange architecture as a solution to this problem.
This technology preserves AI model weights while adding only minimal additional hardware to solve the problems from the conventional research. It reconstructs the conductance values stored in ReRAM cells at the software level and adjusts the dynamic ADC range to minimize unnecessary ADC steps. The technique (1) detects cell values that unnecessarily require high ADC resolution and redistributes them to neighboring cells using the Split-the-Burden (STB) algorithm, and (2) skips redundant ADC steps through the Dynamic ADC Range (DAR) technique based on the reconfigured cell values.
According to the research, OptiRange achieves up to 3 times energy savings and up to 1.4 times speed improvement compared to state-of-the-art (SOTA) models. This research is expected to contribute not only to ReRam-based PIN but reducing ADC energy consumption and latency in a wide range of PIM hardware designs.
▶ Paper title: “OptiRange: An Efficient ReRAM-Based PIM Accelerator with ADC Resolution Optimization”
▶Authors: Ji Ki-san (Second Author, Ph.D. Integrated Program), Kim Young-geon (Third Author, Master’s Program), Park Young-jun (Fourth Author, Master’s Program), Kim Sang-yeon (Fifth Author, Ph.D. Integrated Program), and Professor Ryu Sung-ju (Corresponding Author)