Vertical FerroelectricMetal Field-Effect Transistor (V-FeMFET) With Channel-All-Around (CAA) Structure

초록

HfO2-based ferroelectric field-effect transistors (FeFETs) are promising contenders for nonvolatile memory (NVM) devices due to their CMOS compatibility and scalability. However, conventional metal-ferroelectric (FE)-interfacial layer (IL)-silicon (MFIS) structures often suffer from a limited memory window (MW) and poor program/erase ( P / E ) cycling endurance due to the unfavorable gate potential distribution across the gate-stack. To address these challenges, we propose a novel vertical FE-metal field-effect transistor (V-FeMFET), incorporating a metal-FE-metal-IL-silicon (MFMIS) gate-stack in a vertical channel-all-around (CAA) configuration. By integrating a metal-FE-metal (MFM) capacitor above a cylindrical metal-IL-silicon (MIS) capacitor, the architecture enables an intrinsically small area ratio (AR) between the FE area ( A(FE) ) and the channel area ( A(MIS) ) without sacrificing the device footprint. The memory characteristics of the proposed V-FeMFET were comprehensively analyzed through precisely calibrated technology computer-aided design (TCAD) simulation. By optimizing the AR through spacer thickness engineering, a wide MW of 3.0V was achieved under low-voltage, high-speed P / E pulses (+/- 2V/100ns). Furthermore, the device exhibits a reduced electric field across the IL, which potentially improves the P / E cycling endurance. A rigorous analysis combining load-line analysis and capacitance ratio (CR) evaluations clarified the mechanism behind the MW expansion. These results demonstrate that the V-FeMFET offers significant advantages in terms of MW, reliability, scalability, and back-end-of-line (BEOL) compatibility, positioning it as a promising solution for versatile NVM applications.

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