High-speed monolithic 3D ternary CMOS design with junctionless FETs

초록

A novel monolithic 3D ternary complementary metal-oxide-semiconductor (M3D T-CMOS) inverter is proposed and evaluated for the better operating speed and integration density. It features a monolithically stacked structure with a MOS field-effect transistor (MOSFET) and a balance control transistor (BCT) for the high/low and the intermediate states, respectively. The BCT is composed of junctionless FET which can precisely control the drain current of n- and p-type devices. A contact-in-contact process is adopted for the vertical connections between the MOSFET and BCT, which precisely controls the contact resistance and ensures balanced current distribution between the devices. Therefore, the M3D T-CMOS devices are advantageous to match the current-levels of the both devices between each other. The technology computer-aided design simulation results show that the M3D T-CMOS inverter can achieve a 141 mV static noise margin, indicating stable operation as the ternary logic device. In addition, the ternary states are clearly distinguished even at 10 MHz operating speed.

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