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Write Bias Scheme Optimization of Ferroelectric Field-Effect-Transistor (FeFET) Synapse for Accurate On-chip Training
- Kang, Seungmin;
- Kim, Sangwan;
- Kim, Sihyun
Citations
SCOPUS
0초록
Through technology computer-aided-design (TCAD) simulation and ferroelectric capacitor measurement, we optimized the write bias scheme in on-chip training of HfO2-based ferroelectric field-effect-transistor (FeFET) synapse to improve training accuracy. With the optimized write bias scheme secured in this work, 4-bit synaptic operation was confirmed even in the presence of D2D variations in remanent polarization (Pr) and coercive field (Ec) induced by the ferroelectric film process and the wake-up procedure. © 2024 IEEE.
키워드
Device-to-device variation; FeFET; Ferroelectric; On-chip training; Synapse
- 제목
- Write Bias Scheme Optimization of Ferroelectric Field-Effect-Transistor (FeFET) Synapse for Accurate On-chip Training
- 저자
- Kang, Seungmin; Kim, Sangwan; Kim, Sihyun
- 발행일
- 2024
- 유형
- Conference Paper
- 저널명
- Proceedings - International SoC Design Conference 2024, ISOCC 2024
- 페이지
- 153 ~ 154