Demonstration of Ferroelectric Tunnel Field-Effect Transistor for Low Power Synapse Device

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초록

In this paper, a ferroelectric tunnel field-effect transistor (FeTFET) is demonstrated as a synapse device. The experimental results clearly show that there are several merits in FeTFET as a synapse device comparing with the FeFET. First, the FeTFET shows the similar to 3 orders lower drain current than the FeFET thanks to the different carrier injection mechanism (i.e., band-to-band tunneling). Second, the memory window of FeTFET (1.48 V) is similar to 1.5 times larger than the FeFET (0.95 V) due to an enhanced erase efficiency. As a result, the FeTFET shows the better training accuracy (similar to 91.5% ) even with the similar to 25 times lower energy consumption (similar to 0.16 mJ) comparing with the FeFET (similar to 90.4% accuracy with 4.06 mJ energy consumption). Lastly, the FeTFET shows a good retention property (> 10 years) with a similar to 10(7) endurance characteristic. In short, the FeTFET can be a promising candidate for a low-power synapse device.

키워드

FeFETsSynapsesAccuracyTrainingLogic gatesEnergy consumptionSwitchesSolidsCapacitorsTunnelingSynapse deviceferroelectric tunnel field-effect transistor (FeTFET)erase efficiencymemory windowaccuracylow energy consumption
제목
Demonstration of Ferroelectric Tunnel Field-Effect Transistor for Low Power Synapse Device
저자
Go, SeungwonLee, SunwooSon, JaekyunLee, Dong KeunNoh, HyungjuPark, Jae YeonKim, SeonggeunAhn, HyunhoKim, SihyunKim, Sangwan
DOI
10.1109/TNANO.2025.3595532
발행일
2025
유형
Letter
저널명
IEEE Transactions on Nanotechnology
24
페이지
413 ~ 416