Research Team Led by Ryu Sung-ju, Professor of the Department of System Semiconductor Engineering, Has Paper Accepted at “ICCAD 2026,” a Top Conference in the Field of Semiconductor Design Automation
A paper by the research team led by Professor Ryu Sung-ju from the Department of System Semiconductor Engineering, the Department of Electronic Engineering, and the Department of Semiconductor Engineering at this university has been accepted for presentation at "International Conference on Computer-Aided Design (hereinafter ICCAD) 2026," a top conference in the field of semiconductor design and automation. ICCAD, which began in 1982, is a prestigious international conference that has led advancements in the fields of semiconductor and VLSI (Very Large-Scale Integration) design and related technologies. It is scheduled to be held in San Jose, USA, from November 8 to 12.
The paper is titled “Mosaic: Fast Sparse Matrix Factorization with Parallel Tiling-Merging Computation.” Led by master’s student Ryu Jae-woong, the research was conducted in collaboration with Ki Seong-min (integrated master’s and Ph.D. program), Park Jae-ha (master’s program), and Jeon Sang-kyu (integrated master’s and Ph.D. program).
Sparse matrix factorization is a core technology used in various fields, ranging from engineering simulations to cutting-edge machine learning. While recent advancements in hardware accelerators have significantly improved the speed of the numerical factorization stage, the coarsening process, which simplifies graphs during the symbolic factorization stage, has emerged as a new bottleneck, limiting overall performance improvements.
To address this issue, the research team developed a new hardware accelerator called "Mosaic," which parallelizes the coarsening process by introducing tiling and merging pipelines. In addition, by applying the Selective DGEMM Dropping technique, which selectively omits operations that have minimal impact on the results during the numerical factorization stage, the team succeeded in further increasing computational speed while maintaining accuracy.
The findings show that the proposed Mosaic accelerator achieved an average speedup of 2.31 times for Cholesky decomposition and 1.72 times for LU decomposition compared to existing state-of-the-art hardware accelerators, while maintaining practical numerical accuracy across 28 matrix datasets with diverse characteristics. It also achieved a groundbreaking reduction in computation time of up to 6.74 times. This is expected to contribute to maximizing the efficiency of complex circuit simulations and large-scale optimization computations.
▶ Paper Title: Mosaic: Fast Sparse Matrix Factorization with Parallel Tiling-Merging Computation
▶ Author: Ryu Jae-Woong (First Author), Ki Seong-Min (Second Author), Park Jae-Ha (Third Author), Jeon Sang-Kyoo (Fourth Author), Professor Ryu Seong-Joo (Corresponding Author)
* At the authors’ request, this post may not be published on websites other than the university’s homepage or in the media without the authors’ permission.
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ICCAD 2026 Mosaic Hardware Accelerator, Parallel Tiling-Merging Computation, Sparse Matrix Factorization
The paper is titled “Mosaic: Fast Sparse Matrix Factorization with Parallel Tiling-Merging Computation.” Led by master’s student Ryu Jae-woong, the research was conducted in collaboration with Ki Seong-min (integrated master’s and Ph.D. program), Park Jae-ha (master’s program), and Jeon Sang-kyu (integrated master’s and Ph.D. program).
Sparse matrix factorization is a core technology used in various fields, ranging from engineering simulations to cutting-edge machine learning. While recent advancements in hardware accelerators have significantly improved the speed of the numerical factorization stage, the coarsening process, which simplifies graphs during the symbolic factorization stage, has emerged as a new bottleneck, limiting overall performance improvements.
To address this issue, the research team developed a new hardware accelerator called "Mosaic," which parallelizes the coarsening process by introducing tiling and merging pipelines. In addition, by applying the Selective DGEMM Dropping technique, which selectively omits operations that have minimal impact on the results during the numerical factorization stage, the team succeeded in further increasing computational speed while maintaining accuracy.
The findings show that the proposed Mosaic accelerator achieved an average speedup of 2.31 times for Cholesky decomposition and 1.72 times for LU decomposition compared to existing state-of-the-art hardware accelerators, while maintaining practical numerical accuracy across 28 matrix datasets with diverse characteristics. It also achieved a groundbreaking reduction in computation time of up to 6.74 times. This is expected to contribute to maximizing the efficiency of complex circuit simulations and large-scale optimization computations.
▶ Paper Title: Mosaic: Fast Sparse Matrix Factorization with Parallel Tiling-Merging Computation
▶ Author: Ryu Jae-Woong (First Author), Ki Seong-Min (Second Author), Park Jae-Ha (Third Author), Jeon Sang-Kyoo (Fourth Author), Professor Ryu Seong-Joo (Corresponding Author)
* At the authors’ request, this post may not be published on websites other than the university’s homepage or in the media without the authors’ permission.
[SEO Keyword]
ICCAD 2026 Mosaic Hardware Accelerator, Parallel Tiling-Merging Computation, Sparse Matrix Factorization