Ultrawideband Chip-to-Chip Interconnect Using Bond Wire With Sidewalls

초록

Thisarticlepresentsanovelultrawidebandchip-to-chip interconnect that uses bond wire with sidewalls toaddress the limitations of conventional bond-wire interconnects.These limitations include reduced bandwidth due to parasiticcomponents and potential performance degradation caused bydielectric resonance in the silicon substrate. To overcome theselimitations, the proposed technique utilizes metallic sidewallsaround the bond wire, formed by bumps on a septum, to serve asa ground and compensate for parasitic inductance. Additionally,the characteristic impedance of bond wire is adjusted andmatched to the reference by encapsulating the overall structurewith molding epoxy, which also functions as interconnect pro-tection. A metallic septum isolates two silicon chips electromag-netically and removes dielectric resonances from the frequencyrange of near dc to 170 GHz. To validate the effectiveness of theproposed technique, two silicon CMOS chips consisting of 50-microstrip lines were interconnected using the conventional andproposed bond-wire interconnects. The on-wafer measurementsdemonstrated a significant improvement of the proposed inter-connects in insertion and return losses for chip spacings ofboth 200 and 500 mu m. Specifically, for a chip spacing of 500 mu m,the overall structure using the proposed interconnect exhibitedan average insertion loss of 3.7 dB across the range ofD-band(110-170 GHz), which is 5.0 dB lower than the conventional bond-wire interconnect. Return loss was better than 13.4 dB across arange from near dc to 170 GHz. The proposed wire interconnectsexhibited a net loss of less than 2.0 dB up to 170 GHz, estimatedby subtracting the measured loss of microstrip lines on the CMOSchips. To the best of our knowledge, this is the first demonstrationof a silicon chip-to-chip interconnect using bond wire with a 3-dBbandwidth greater than 170 GHz

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