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Development of Multi-Chain Tapped-delay Line Based TDC Using Down Sampling Method for Minimizing FPGA Resources
- 제목
- Development of Multi-Chain Tapped-delay Line Based TDC Using Down Sampling Method for Minimizing FPGA Resources
- 저자
- 최용
- 발행일
- 2024-10-30
- 학회명
- 2024 IEEE NUCLEAR SCIENCE SYMPOSIUM AND MEDICAL IMAGING CONFERENCE