A Position Decoder Circuit for PET Detector with Different Physical Properties

초록

We have reported the usefulness of a channel reduction circuit, called "position decoder circuit (PDC)" generating the digital address and analog pulse of an interacted channel among many PET detector outputs. However, in a previous study, we focused on the design of a PDC dedicated to a GAPD-based PET detector with a fast scintillator. The goal of this study was to develop a PDC that could be generally utilized to the various PET detector modules having different physical properties. A PDC, based on two-stage (32:1 and 8:1) channel reduction architecture, was designed. The PDC consisted of: (1) GAPD bias voltage and signal gain adjustment circuits to correct the non-homogeneity and different characteristics of the input signals; (2) a low level discrimination circuit, to reject noise or scatter signals; (3) an analog signal delay and switch circuits to output an analog pulse corresponding to the interacted channel; and (4) a FPGA circuit to identify a valid channel and providing a digital address. Two different types of PET detector modules, LYSO-GAPD (high light output and fast decay time) and BGO-GAPD (low light output and slow decay time), were constructed to evaluate the functionality of the developed PDC. The developed PDC successfully identified the interacted channel. Channel address/analog pulse output signals were generated after 34 ns/98 ns for LYSO-GAPD and 50 ns/98 ns for BGO-GAPD compared with input signals, respectively. Measured energy and coincidence timing resolutions for LYSO-GAPD were 18.5% and 2.9 ns, respectively, and for BGO-GAPD, 20% and 7.8 ns, respectively. A hot-rod phantom image of the proof-of-principle PET system consisting of 8 pairs of PET detector modules was successfully acquired. Experimental results indicate that the PDC developed in this study is useful to identify a valid channel among a large number of readout channels of the PET detectors with different physical properties.