A Second-order Delta-sigma Modulator for Battery Management System DC Measurement

초록

This paper presents a second-order modified feed-forward (FF) delta-sigma modulator for battery management system DC measurement. The proposed ADC employs a modified 3-bit feedback digital-to-analog converter (DAC) with the data weight averaging (DWA) technique to improve the capacitance matching. The modified 3-bit DAC reduces the logic complexity of the DWA by simplifying the switching network of unit capacitors. Additionally, the proposed ADC adopts capacitor swapping technique between the input and reference sampling capacitors to minimize its gain error. To further improve the performance of the proposed ADC, system-level low- frequency chopping (CHL) and correlated double sampling (CDS) are employed to mitigate offset and flicker noise. The prototype ADC is fabricated in a 180 nm CMOS process, and the core area is 0.53 mm(2). It consumes 9.48 mu W from a 1.8 V supply voltage at an operating clock frequency of 19.2 kHz with an oversampling ratio (OSR) of 256. It achieves a dynamic range (DR) of 102.4 dB, a resolution of 7 mu V-rms, and an offset of 6.86 mu V, resulting in a Schreier figure-of-merit (FoM) of 165.3 dB.

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