A 0.93-μW Single-Stage Rail-to-Rail Class AB Buffer Amplifier Improving DC gain and Slew-Rate with Different-Ratio Current-Mirrors and Positive-Feedback Loops

  • Cho, Joo-Mi
  • Park, Hyo-Jin
  • Hong, Sung-Wan
Citations

SCOPUS

3

초록

This paper presents a rail-to-rail class AB single-stage buffer amplifier to drive a capacitive load (Co). To achieve a high DC gain and a high slew-rate (SR), the proposed amplifier uses different-ratio current-mirrors (DRCMs) and positive feedback loops (PFLs). The proposed amplifier drives a wide range of Co over 0.15-15 nF owing to the single-stage structure. A prototype chip was fabricated in a 0.18-μm CMOS process and occupies an area of 0.014 mm2. © 2021 JSAP.

제목
A 0.93-μW Single-Stage Rail-to-Rail Class AB Buffer Amplifier Improving DC gain and Slew-Rate with Different-Ratio Current-Mirrors and Positive-Feedback Loops
저자
Cho, Joo-MiPark, Hyo-JinHong, Sung-Wan
DOI
10.23919/VLSICircuits52068.2021.9492475
발행일
2021-06-13
유형
Conference Paper
저널명
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
2021-June