A 0, 0);'>1.0 V 77.5 dB Dynamic Range Delta-sigma ADC using Op-Amp Bias Sharing Technique

  • Kwak, Yong-Sik
  • Yun, Min-Ho
  • Lee, Seung-Hoon
  • Ahn, Gil-Cho
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초록

A second-order single-bit delta-sigma analog-to-digital converter (ADC) is presented in this paper. An op-amp bias sharing technique is used to reduce the power consumption and active area of the ADC. It achieves 77.5 dB dynamic range over 1 kHz signal bandwidth with an oversampling ratio of 512. The total power consumption of the proposed ADC is 27.1 mu W from a 1.0 V power supply. The prototype chip occupies 0.16 mm(2) using a 0.13 mu m CMOS technology.

키워드

Delta-sigma modulatoranalog-to-digital converterdynamic biasinglow-voltageopamp bias sharing techniqueMODULATOR
제목
A 0, 0);'>1.0 V 77.5 dB Dynamic Range Delta-sigma ADC using Op-Amp Bias Sharing Technique
저자
Kwak, Yong-SikYun, Min-HoLee, Seung-HoonAhn, Gil-Cho
DOI
10.5573/JSTS.2018.18.3.346
발행일
2018-06
유형
Article
저널명
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
18
3
페이지
346 ~ 351