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A 0, 0);'>1.0 V 77.5 dB Dynamic Range Delta-sigma ADC using Op-Amp Bias Sharing Technique
- Kwak, Yong-Sik;
- Yun, Min-Ho;
- Lee, Seung-Hoon;
- Ahn, Gil-Cho
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1초록
A second-order single-bit delta-sigma analog-to-digital converter (ADC) is presented in this paper. An op-amp bias sharing technique is used to reduce the power consumption and active area of the ADC. It achieves 77.5 dB dynamic range over 1 kHz signal bandwidth with an oversampling ratio of 512. The total power consumption of the proposed ADC is 27.1 mu W from a 1.0 V power supply. The prototype chip occupies 0.16 mm(2) using a 0.13 mu m CMOS technology.
키워드
Delta-sigma modulator; analog-to-digital converter; dynamic biasing; low-voltage; opamp bias sharing technique; MODULATOR
- 제목
- A 0, 0);'>1.0 V 77.5 dB Dynamic Range Delta-sigma ADC using Op-Amp Bias Sharing Technique
- 저자
- Kwak, Yong-Sik; Yun, Min-Ho; Lee, Seung-Hoon; Ahn, Gil-Cho
- 발행일
- 2018-06
- 유형
- Article
- 권
- 18
- 호
- 3
- 페이지
- 346 ~ 351