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A 0.8-1.5GHz ADPLL Design using a 1-step Vernier TDC

제목
A 0.8-1.5GHz ADPLL Design using a 1-step Vernier TDC
저자
범진욱
발행일
2016-10-24
학회명
2016 ISOCC CHIP DESIGN CONTEST

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