A Compact Single-Stage Input and Output Rail-to-Rail Class AB Buffer Amplifier With an Asymmetric Output Structure

  • Oh, Young-Ju
  • Jeong, Hyun-Woo
  • Park, Hyeonho
  • Shin, Jeeyoung
  • Jeong, Junwon
  • 외 2명
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초록

This letter presents a compact single-stage buffer amplifier designed to drive a wide range of capacitive loads (C<inf>L</inf>). To further reduce power consumption and silicon area compared to previous single-stage rail-to-rail amplifiers, this letter proposes an asymmetric rail-to-rail class AB output structure. To achieve a high slew rate, the proposed amplifier employs positive feedback loops and a dynamic floating node. A prototype chip successfully drove a wide range of C<inf>L</inf>, from 250 pF to 15 nF, while achieving a fast transient response. The chip was fabricated using a 0.18-µm CMOS process. © 2018 IEEE.

키워드

Class-ABcompact single-stage buffer amplifier (AMP)high slew rate (SR)input and output rail-to-railwide range capacitive load
제목
A Compact Single-Stage Input and Output Rail-to-Rail Class AB Buffer Amplifier With an Asymmetric Output Structure
저자
Oh, Young-JuJeong, Hyun-WooPark, HyeonhoShin, JeeyoungJeong, JunwonChoi, WoongHong, Sung-Wan
DOI
10.1109/LSSC.2025.3551357
발행일
2025
유형
Article
저널명
IEEE Solid-State Circuits Letters
8
페이지
73 ~ 76