A 10b 100MS/s 25.2mW 0.18μm CMOS ADC With Various Circuit Sharing Techniques

초록

This work describes a 10b 100MS/s 0.18 mu m CMOS three-stage pipeline ADC. Two MDACs share an op-amp without MOS switches connected in series while removing a memory effect. Three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC with an active die area of 0.80mm(2) shows DNL and INL within 0.58LSB and 0.94LSB, respectively, and consumes 25.2mW at 1.8V and 100MS/s.

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