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A 10b 100MS/s 25.2mW 0.18μm CMOS ADC With Various Circuit Sharing Techniques
- Park, Beom-Soo;
- Ji, Seung-Hak;
- Choi, Min-Ho;
- Lee, Kyung-Hoon;
- Ahn, Gil-Cho;
- 외 1명
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4초록
This work describes a 10b 100MS/s 0.18 mu m CMOS three-stage pipeline ADC. Two MDACs share an op-amp without MOS switches connected in series while removing a memory effect. Three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC with an active die area of 0.80mm(2) shows DNL and INL within 0.58LSB and 0.94LSB, respectively, and consumes 25.2mW at 1.8V and 100MS/s.
키워드
circuit sharing; low power; small size; ADC; PIPELINED ADC; 50-MS/S
- 제목
- A 10b 100MS/s 25.2mW 0.18μm CMOS ADC With Various Circuit Sharing Techniques
- 저자
- Park, Beom-Soo; Ji, Seung-Hak; Choi, Min-Ho; Lee, Kyung-Hoon; Ahn, Gil-Cho; Lee, Seung-Hoon
- 발행일
- 2009
- 유형
- Proceedings Paper
- 저널명
- 2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009)
- 페이지
- 329 ~ 332