A Digitally Enhanced Low-Distortion Delta-Sigma Modulator for Wideband Application

초록

A delta-sigma modulator with digital signal feed-forward architecture is presented. Digital domain summation which is favorable in high speed operation is adopted in the proposed modulator by employing extra quantizers in each signal path. Additional quantization noise from the extra quantizers is effectively eliminated by digital cancellation logic. The prototype chip, fabricated in a 0.13 mu m CMOS process, achieves a dynamic range (DR) of 74.6 dB and a peak signal-to-noise and distortion ratio (SNDR) of 67.6 dB for a 1.25 MHz signal bandwidth with an 80 MHz clock frequency. The total power consumption is 9.13mW at a 1.2 V supply voltage.

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