A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling

초록

This paper presents a 10-bit 900-MS/s single-channel pipelined successive approximation register (SAR) analog-to-digital converter (ADC). A multiplying digital-to-analog converter (MDAC) using an open-loop amplifier is employed to increase the conversion speed efficiently. To reduce the complexity of the calibration logic for non-ideal open-loop gain stage, a reference scaling technique is adopted. A second stage 5-bit SAR ADC is implemented in current-mode with a gm-cell residue amplifier. The prototype ADC is fabricated in a 28 nm FDSOI CMOS process with an active die area of 0.014 mm(2). Operating at 900-MS/s, the ADC achieves a signal-to-noise and distortion ratio of 48.9 dB and a spurious-free dynamic range of 61.2 dB, at Nyquist. It consumes 9.56 mW at a 1.0/1.2 V supply voltage, resulting in a Nyquist figure of merit of 46.7 fJ/conversion-step.

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