12b 50 MS/s 0.18 μm CMOS ADC with highly linear input variable gain amplifier

초록

A 12b 50 MS/s 0.18 mu m CMOS ADC with a highly linear variable gain amplifier (VGA) for medical ultrasound and CCD image sensor applications is presented. The proposed four-step pipeline ADC optimises power and chip area at target specifications while the front-end VGA, based on a conventional approximated log function, employs a merged capacitor switching scheme to improve the VGA gain linearity. The proposed input VGA shows a linearity error less than 0.013 dB in a gain range from -3 to 0 dB by a 0.2 dB step. The measured prototype ADC with an active die area of 1.09 mm(2) shows a maximum SNDR and SFDR of 62.6 and 73.1 dB, respectively, and consumes 28.1 mW at 1.8 V and 50 MS/s.