A 12-bit 40-kS/s VCM-Based Switching C-C SAR ADC

초록

A 12-bit 40-kS/s V-CM-based switching C-C successive approximation register (SAR) analog-to-digital converter (ADC) is presented. The proposed SAR ADC exploits V-CM-based switching method with a C-C segmented digital-to-analog converter (DAC) to reduce the size of the converter. Capacitive sub-DAC with buffer amplifier using offset cancellation is utilized to enhance the linearity of converter. Majority vote comparison technique is employed to alleviate comparator noise and to achieve high accuracy comparison. The prototype ADC is fabricated in a 0.18 mu m CMOS process. The ADC shows maximum SNDR and SFDR of 57.1dB and 57.3dB with a 1.8V supply while consuming 66.7 mu W. It occupies an active die area of 0.22mm(2).

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