High-Level Synthesis Considering Layer Assignment on Timing in 3D-IC

초록

As the integrated circuit (IC) technology scales to a single-nanometer regime, three-dimensional (3D) IC structure is applied increasingly with through silicon via (TSV) and stacking technologies. In this paper, we propose a method of considering layer assignment in high-level synthesis (HLS). To cope with unexpected delays due to different layer placement, the candidate of TSV location is calculated with force-directed scheduling, one of the HLS algorithms, before placement. In the experimental results, the latency of the proposed method is compared with the previous method.

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