Power Supply Noise Reduction by Clock Scheduling with Gate-Level Current Waveform Estimation

초록

As technology progresses, power supply noise, such as IR-drop and L*di/dt drop, has become a major concern in power distribution network design. Since power supply noise is fundamentally caused by large current peaks, it can be minimized in early stages by deliberate clock scheduling which utilizes nonzero clock skew and does not violate timing constraints. In this paper, we propose a clock skew scheduling method to reduce power supply noise by minimizing the peak current. While previous approaches require extra characterization efforts to estimate supply current waveform of circuits, we approximate gate-level current waveform only with existing cell library information. Experimental results show that our method can reduce the peak current by 11.6% on average and the voltage variation in power lines by 18.3% on average.

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