A Compact Photocurrent Recording IC With High-Linearity Dual PWM Buffered R-DACs

초록

This article introduces a photocurrent recording front-end, emphasizing both energy efficiency and compact size. The proposed front-end circuit comprises a voltage-controlled oscillator-based quantizer (VCOQ) and a digital low-pass filter for feedback current, optimizing conversion efficiency. Furthermore, a dual pulse-width modulation (PWM)-based buffered resistive digital-to-analog converter (R-DAC) is employed for enhanced linearity and area efficiency. The PWM logic, implemented with a digital counter instead of conventional structures, reduces dynamic power requirements. Additionally, integrating a coarse R-DAC with extended bit depth into the digital filter feedback loop significantly enhances dynamic range (DR). The proposed architecture is further reinforced by loop gain calibration and a fast-settling feedforward path to mitigate parasitic effects on the passive integrator and reduce the data loss due to saturation caused by rapid input current fluctuations. Fabricated in a 90 nm CMOS process, the prototype chip occupies 0.067 mm(2) and achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 87.66 dB, with an energy efficiency of 0.188 pJ/conv. Furthermore, a DR of 144 dB is attained through the DR extension loop.

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