A 10b 50MS/s 90nm CMOS Skinny-Shape ADC Using Variable References for CIS Applications

초록

This work proposes a skinny-shape 10b 50MS/s 90nm CMOS four-step pipeline ADC for various CIS applications. The proposed ADC converts analog signals in variable signal-swing ranges of 1.12 to 1.60Vp-p into low voltage-based digital data. The proposed on-chip I/V reference circuits generate the required variable reference voltages with a fixed common-mode level using a single external control voltage. The prototype ADC implemented in a 90nm CMOS process shows a maximum SNDR and SFDR of 55.1dB and 65.6dB, respectively. The ADC with an active die area of 0.23mm(2) consumes 17.5mW at 50MS/s using dual supply voltages of 2.5V for analog and 1.2V for digital.

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