Interleaving buffer insertion and transistor sizing into a single optimization

초록

This work presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs, The purpose of this work is to examine how combining a sizing algorithm with buffer insertion will help us achieve better area-delay or power-delay tradeoffs, and to determine where and when to insert buffers in a circuit. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-Iike gate sizing algorithm alone, as is illustrated by several area-delay tradeoff curves shown in this paper.

키워드