A Two-Step ADC with a Separate DAC Method for Enhanced Sub-Quantizer Settling Condition

초록

This paper presents a 12-bit 10 MS/s two-step ADC that utilizes an asynchronous SAR sub-quantizer. To enhance the conversion speed by using a smaller unit capacitance, a separate C-DAC is employed for the sub-quantizer, independent of the one used for residue amplification. This ultimately enhances the SAR operation speed of the coarse stage. In addition, the proposed ADC shares the sub-quantizer for both the coarse and fine bit conversion processes, and it consequently reduces the ADC core area. The prototype ADC fabricated in a 180nm CMOS process achieves measured DNL and INL within 0.24LSB and 0.87LSB at 12-bit resolution, respectively. The measured SNDR and SFDR are 69.1dB and 79.0dB at 10MS/s, respectively. The ADC occupies a core area of 0.19mm2 and consumes 2.71mW at a 1.8V supply. © 2025 IEEE.

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