A 1.1 V 82.3dB Audio ΔΣ ADC Using Asynchronous SAR Type Quantizer

초록

A switched-capacitor second-order audio.S analog-to-digital converter (ADC) is presented. The proposed.S ADC employs low-distortion input feed-forward architecture to relax the linearity requirement of the integrators. A 4-bit asynchronous successive approximation register (SAR) type internal quantizer is used for power efficient design by incorporating the analog adder with the quantizer. A tree-structured dynamic element matching (DEM) technique is employed to reduce the distortion resulted from the capacitor mismatch in the feedback digital-to-analog converter (DAC). The prototype Delta Sigma ADC implemented in a 45nm CMOS process achieves 85.4 dB peak signal-to-noise ratio (SNR), 82.3 dB peak signal-to-noise and distortion ratio (SNDR) and 98.1 dB dynamic range (DR) for a signal bandwidth of 24 kHz while consuming 517.4 mu W at 1.1 V supply voltage.