A 0.9V 0.022mm<SUP>2</SUP> 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique

  • Kwak, Yong-Sik
  • Kim, Ho-Jin
  • Cho, Kang-, II
  • Boo, Jun-Ho
  • Ahn, Gil-Cho
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초록

Switched-capacitor (SC) circuits have been widely used for sampling operation of mixed-signal integrated circuits, especially in CMOS technologies. Using with amplifiers, SC circuits enable the robust implementation of the sampling network with various transfer functions. However, the kT/C noise resulting from the transistors used for switches limits the achievable signal-To-noise ratio (SNR). Therefore, achieving wide dynamic range (DR) requires a large amount of on-chip sampling capacitance. In [1], a continuous-Time input stage is employed to achieve the kT/C noise free operation, which leads to considerable power and area reduction. However, the capacitive coupling used at the input will block DC signals and limit the range of suitable applications. © 2021 IEEE.

제목
A 0.9V 0.022mm<SUP>2</SUP> 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique
저자
Kwak, Yong-SikKim, Ho-JinCho, Kang-, IIBoo, Jun-HoAhn, Gil-Cho
DOI
10.1109/A-SSCC53895.2021.9634767
발행일
2021
유형
Proceedings Paper
저널명
IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021)