A Computing-In-Memory Analog Popcount Circuit Utilizing 9T-SRAM

초록

This paper proposes a computing-in-memory analog pop count circuit design leveraging logic operations within SRAM to achieve energy-efficient Multiply-and-Accumulate (MAC) op-erations. The hardware design employs a MAC scheme that simplifies multi-bit MAC computations by using popcount op-erations combined with shift and accumulate techniques. This approach effectively mitigates the power consumption overhead traditionally associated with analog circuitry required for multi-bit MAC processing. The proposed architecture integrates the 9T SRAM bitcells for efficient computation of the AND operations between input and weight bits, followed by an analog popcount circuit to determine the pop count. Simulations conducted on 28nm CMOS technology demonstrates that the proposed design achieves an energy efficiency of 6.4 TOPSIW. © 2025 IEEE.

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