Stochastic glitch estimation and path balancing for statistical optimization

초록

Statistical power optimization using the probabilistic delay model is introduced in this paper. We propose a new method for power optimization that uses path balancing based on stochastic estimation of glitch in Statistical Static Timing Analysis (SSTA). The proposed method estimates the probability of glitch occurrence using tightness probability of each node in timing graph. In addition, we propose efficient gate sizing technique for glitch reduction using accurate calculation of sizing effect in delay considering probability of glitch occurrence. The efficiency of the proposed method has been verified on ISCAS85 benchmark circuits with 0.16 mu m model parameters. Experimental results show up to 8.6% of accuracy improvement in glitch estimation and 9.5% of optimization improvement.