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초록
This paper presents a 92.4%-peak-efficiency 48V to 0.8-to-1.6V hybrid converter based on an inductor-interleaved Fibonacci switched-capacitor (I2-FSC). The proposed converter reduces ΔVL with few flying capacitors, thereby achieving a high duty cycle under ultra-low VCRs and reducing ACR loss. It also minimizes switching and conduction losses, while current distribution lowers DCR loss and a fixed 0.5 duty in the capacitive path reduces VO ripple. The chip is fabricated in a 180nm BCD process. © 2026 IEEE.
- 제목
- A 92.4%-Peak-Efficiency 48V to 0.8-to-1.6V Hybrid Converter with Inductor-Interleaved Fibonacci Switched-Capacitor
- 저자
- Jeong, Hyun-Woo; Lee, Chan-Ho; Choi, Hyeon-Ji; Hong, Sung-Wan
- 발행일
- 2026-02
- 유형
- Proceedings Paper
- 저널명
- Digest of Technical Papers - IEEE International Solid-State Circuits Conference
- 권
- 69
- 페이지
- 456 ~ 458