12 b 50 MS/s 0.18 μm CMOS SAR ADC based on highly linear C-R hybrid DAC

초록

A 12 b 50 MS/s successive-approximation register (SAR) ADC with a highly linear C-R hybrid DAC is presented. The proposed DAC significantly reduces the required total number of unit capacitors by processing the upper bits based on a binary-weighted capacitor array and the remaining lower bits based on reference segment voltages, which are obtained from a simple resistor string. The reduced number of unit capacitors enables the use of larger unit capacitance, resulting in improved matching accuracy. In the C-R hybrid DAC, an input range scaling technique, which matches a full-scale input range to the reference voltage range, implements the binary-weighted SAR operation without additional capacitors and reference voltages. The DAC linearity is improved considerably through the process-insensitive capacitor-array layout, which cancels out oxide-gradient errors. The prototype ADC in a 0.18 mu m CMOS process demonstrates measured differential and integral non-linearities within 0.71 LSB and 0.85 LSB at 12 b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 64.3 and 74.7 dB at 50 MS/s, respectively. The ADC occupies an active die area of 0.17 mm(2) and consumes 2.63 mA with a 1.8 V supply voltage.