A 12-bit 3-MS/s Synchronous SAR ADC With a Hybrid RC DAC

초록

This paper presents a 12-bit, 3-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To decrease the number of unit capacitors, a hybrid RC digital-to-analog converter (DAC) is employed. The prototype ADC is fabricated with 3.3V devices in an 80nm CMOS process. The ADC exhibits differential nonlinearity (DNL) and integral nonlinearity (INL) values that are both less than 0.73 LSB and 1.19 LSB, respectively. At 3MHz sampling frequency, the prototype ADC attains 67.1dB SNDR and 78.6dB SFDR for a 0.01MHz input sine wave with a 3.3V supply while consuming 4.63mW power.

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