Symmetrical Buffered Clock Tree Synthesis considering NBTI

초록

A clock tree synthesis (CTS) has become a crucial step in a high performance synchronous system. Clock gating technique is an efficient method for reducing power consumption. However, it unevenly impacts negative bias temperature instability (NBTI)-induced V-th degradation of clock buffers. Thus, it may cause asymmetric aging resulting in a large clock skew. In this work, we propose a novel symmetrical buffered clock tree synthesis with supply voltage alignment for handling NBTL Our CTS estimates asymmetric NBTI caused by clock gating through signal probability. We formulate the skew minimization problem based on linear programming which determines optimal SVs of buffers. Then, we align supply voltages (SVs) on buffers while satisfying skew constraints after years of aging. Wire routing is performed using wire snaking to complete the clock tree. Experiment results show that the proposed CTS achieves on average 35.5% reduction in clock skew compared to existing CTS methods after 10 years of NBTI degradation.

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