A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC

초록

This brief presents a single-loop third-order discrete-time delta-sigma (?S) analog-to-digital converter (ADC). The proposed ?S ADC employs source-follower (SF) based open-loop switched-capacitor (SC) integrators to achieve high-speed operation with efficient power consumption. A modified feed-forward topology is proposed to improve the linearity of the modulator using the SF-based integrators. An interpolating 4-bit flash quantizer with an embedded data weighted averaging (DWA) function is employed to address the nonlinearity of the feedback digital-to-analog converter (DAC) for high speed operation. The prototype ADC implemented in a 65nm CMOS technology achieves 75.4-dB dynamic range (DR) and 73.3-dB peak signal-to-noise-and-distortion ratio (SNDR) over 10-MHz bandwidth with an oversampling ratio (OSR) of 16. The power consumption of the modulator is 13.3-mW from a 1.1-V supply, resulting in the Walden and Schreier figure-of-merits (FoMW and FoM(S)) of 174-fJ/conversion-step and 164-dB, respectively.

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