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24Gb/s Inverter-Based CTLE Optimized for Minimal Parasitic Capacitance in 28nm CMOS

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24Gb/s Inverter-Based CTLE Optimized for Minimal Parasitic Capacitance in 28nm CMOS
저자
범진욱
발행일
2025-01-13
학회명
2025 반도체 공학회 동계 학술대회

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