A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR Logic

초록

An ultra-low-power 12-bit 200MS/s two-step pipelined SAR ADC is presented. In the first-stage SAR ADC, a separate DAC is applied with very small unit capacitors which generate the comparator decision threshold, thereby minimizing the required switching power. The dynamic register, which stores the comparator output, directly controls the DAC switch, dramatically reducing the SAR decision delay time. Based on the employed asynchronous SAR logic, the metastable state detection and correction logic can be implemented using a very simple digital logic. The prototype ADC in a 28nm CMOS process achieves a maximum SNDR of 64.8dB, resulting in a FoM of 7.7fJ/conversion-step.

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