A 14-10 b dual-mode low-noise pipeline ADC for high-end CMOS image sensors

초록

This work proposes a low-noise four-stage pipeline ADC operating at 14 b 50 MS/s and 10 b 70 MS/s for high-end CIS applications. In the 10 b 70 MS/s mode, the last-stage MDAC and flash ADC are turned off rather than the first-stage MDAC and flash ADC for the same input-referred noise in both modes. The proposed ADC shares a single amplifier for the first- and second-stage MDACs to reduce power consumption and chip area. The amplifier thermal noise of the SHA and MDACs is minimized by adjusting the trans-conductance of input and current-source transistors while two separate reference voltage drivers for the MDACs and the flash ADCs reduce the switching noise. The prototype ADC in a 0.13 mu m CMOS technology providing 0.35 mu m thick-gate-oxide transistors shows the measured DNL and INL within 0.79 and 2.54 LSB in the 14 b mode, and 0.53 and 0.44 LSB in the 10 b mode, respectively. The ADC shows the maximum SNDR and SFDR of 68.5 and 86.7 dB in the 14 b 50 MS/s mode, and the SNDR and SFDR of 60.5 and 77.8 dB for the 10 b 70 MS/s mode, respectively. The ADC with the measured input-referred noise of 1.20 LSBrms/14 b consumes 192.9 mW at the 14 b 50 MS/s, and 184.9 mW in the 10 b 70 MS/s mode with 3.3/1.2 V dual supplies.

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