A Multi Gbps 10-PAM Receiver in 0.18um CMOS Technology

초록

We report a receiver for ten-level pulse-amplitude modulated(10-PAM) encoded data signals, which was measured to receive data at 8 Gb/s at a maximum frequency(2 GHz). To increase data bit-rate and reduce BER, we designed this circuit by using a current mode amplifier, high speed comparator and a current-mode logic (CML) circuit. The 10-PAM receiver is designed in 0.18-mu m CMOS technology. The measured current consumption is 61mA from 1.8-V supply, and the active chip area is 0.5 x 0.6 mm(2).

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