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A 0.8 - 1.4 GHz ADPLL Design using mismatch TDC without delay cell line in 180nm CMOS

제목
A 0.8 - 1.4 GHz ADPLL Design using mismatch TDC without delay cell line in 180nm CMOS
저자
범진욱
발행일
2018-01-25
학회명
2018 ICEIC

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