A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Sturdy MASH Delta-Sigma Modulator Using Source-Follower-Based Integrators

  • Kwak, Yong-Sik; 
  • Cho, Kang-Il; 
  • Kim, Ho-Jin; 
  • Lee, Seung-Hoon; 
  • Ahn, Gil-Cho
Citations

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3
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6

초록

This paper presents a 2-2 discrete-time sturdy multi-stage noise-shaping (SMASH) delta-sigma modulator using source-follower-based open-loop integrators. The resolution of the SMASH delta-sigma modulator is enhanced by eliminating the first-stage quantization noise from the output. Using the proposed source-follower-based open-loop integrator, the operating speed of the modulator is efficiently improved. The prototype delta-sigma modulator fabricated in a 65-nm CMOS process achieves a 75.8-dB dynamic range and 72.9-dB SNDR in a 20-MHz bandwidth. The modulator occupies an active area of 0.34 mm(2), and its total power consumption is 20.4 mW from a 1.2-V supply voltage operating at a 500-MHz clock frequency.

키워드

analog-to-digital converter (ADC); discrete-time (DT); delta-sigma; multi-stage noise-shaping (MASH); open-loop integrator; source-follower; ADC
제목
A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Sturdy MASH Delta-Sigma Modulator Using Source-Follower-Based Integrators
저자
Kwak, Yong-Sik; Cho, Kang-Il; Kim, Ho-Jin; Lee, Seung-Hoon; Ahn, Gil-Cho
DOI
10.1109/ASSCC.2017.8240273
발행일
2017-12-26
유형
Proceedings Paper
저널명
2017 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)
권
2017-January
페이지
289 ~ 292