Calibration-free 14b 70MS/s 0.13 μm CMOS pipeline A/D converters based on high-matching 3D symmetric capacitors

초록

A 14b 70MS/s pipeline A/D converter (ADC) in a 0.13 mu m CMOS process employs signal insensitive 3D fully symmetric capacitors for high matching accuracy without any calibration scheme. The prototype ADC with a die area of 3.3 mm(2) shows measured differential and integral nonlinearities of 0.65LSB and 1.80LSB, respectively, at 14b.