A 6.25 MHz BW 8-OSR Fifth-Order Single-Stage Sigma-Delta ADC

초록

A switched-capacitor single-stage sigma-delta ADC with a fifth-order modulator is proposed. The proposed sigma-delta ADC employs feed-forward architecture with oversampling ratio (OSR) of 8. The modulator input signal range is extended beyond the full scale of the quantizer with proper coefficients scaling and internal DAC reference scaling. A 19-level quantizer with data weighted averaging dynamic element matching (DWA DEM) technique is employed to improve the linearity of a multi-bit DAC. The prototype ADC fabricated in a 0.13-mu m CMOS technology achieves 63.7 dB SNDR with 1 MHz input signal over 6.25 MHz signal bandwidth while consuming 52.5 mW with the clock frequency of 100 MHz.

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