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A 0.8 – 1.4 GHz ADPLL Design using mismatch TDC without delay cell line in 0.18um CMOS

제목
A 0.8 – 1.4 GHz ADPLL Design using mismatch TDC without delay cell line in 0.18um CMOS
저자
범진욱
발행일
2019-02-14
학회명
2019 한국반도체학술대회

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