A 14b 100MS/s 3.4mm<SUP>2</SUP> 145mW 0.18um CMOS pipeline A/D converter

초록

This work proposes a 14b 100MS/s 0.18um CMOS ADC for the fourth-generation mobile communication systems. The proposed 3-stage pipeline ADC, whose architecture is verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two NWACs, and a back-end 6b subranging flash ADC based on open-toop offset sampling and interpolation to obtain a small chip area at 6b. The prototype ADC implemented in a 0.18um CMOS technology demonstrates the measured DNL and INL within 1.03L-SB and 5.47LSB, respectively, while the ADC shows an SNDR of 59dB and an SFDR of 72dB with an active die area of 3.4mm(2) and a power consumption of 145mW at 100MS/s and 1.8V.

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