A 19.5 ps-LSB Vernier-type Time-to-digital Converter for PET

  • Kim, Min-Sik
  • Cho, Kang-Il
  • Kwak, Yong-Sik
  • Lee, Sangwon
  • Choi, Jaewoo
  • ... Ahn, Gil-Cho
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초록

This paper presents a 19.5 ps-LSB vernier-type time-to-digital converter (TDC) to measure the time of flight in a positron emission tomography (PET) imaging system. An 8x8 SiPMs sensor array coupled to LYSO (Lutetium Yttrium Orthosilicate) scintillator crystals are utilized with an anger logic readout circuit to reduce the total number of analog front-end (AFE) channels. The proposed TDC consists of a 5-bit MSB counter and a 6-bit LSB vernier delay line (VDL) TDC that is controlled by an internal delayed-locked loop. A phase-locked loop is integrated for frequency multiplication to increase the time resolution. The prototype chip is fabricated in a 0.18 mu m CMOS technology. The measured timing resolutions of the prototype TDC are 400ps with a 333 kHz external input and 5ns using a Na-22 point gamma-ray source with an 8x8 SiPMs sensor array and anger logic readout circuit. The prototype TDC consumes 180 mW with a 1.8 V supply voltage while occupying a 1.76 mm(2) of the active area.

키워드

Positron emission tomography (PET)time-to-digital converter (TDC)time of flight (TOF)phase-locked loop (PLL)delay-locked loop (DLL)vernier delay line (VDL)anger logicDELAY-LINETDCPLL
제목
A 19.5 ps-LSB Vernier-type Time-to-digital Converter for PET
저자
Kim, Min-SikCho, Kang-IlKwak, Yong-SikLee, SangwonChoi, JaewooAhn, Gil-Cho
DOI
10.5573/JSTS.2017.17.6.800
발행일
2017-12
유형
Article
저널명
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
17
6
페이지
800 ~ 805