A 1V 20.7μW Four-Stage Amplifier Capable of Driving a 4-to-12nF Capacitive Load with >1.07MHz GBW with an Improved Active Zero

초록

This paper proposes a four-stage amplifier with a wider gain bandwidth (GBW) and less sensitivity to gain reduction caused by process scale down. To widen GBW, the proposed amplifier uses a passive zero in the main path and an improved active zero in the feed-forward path. The amplifier achieves DC gain >120dB, GBW of 1.25 MHz and 1.07 MHz, and 68.5° and 52°, at CL of 4 nF and 12 nF, respectively. The chip is implemented in a 0.18-μ m CMOS process. © 2023 JSAP.