A 12.5-Gb/s Switched Capacitor Based Two Tap DFE With High BER Performance

Cho, Yosep; Park, Jongmin; Burm, Jinwook

doi:10.1109/ISOCC56007.2022.10031329

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A 12.5-Gb/s Switched Capacitor Based Two Tap DFE With High BER Performance

Cho, Yosep;
Park, Jongmin;
Burm, Jinwook

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초록

This paper designs a 2-tap direct decision feedback equalizer (DFE) based on switched-capacitor. It was confirmed that the DFE receiver operates error-free from the data rate of 12.5Gb/s and high channel loss. We obtained Max Eye Height 998.34 mV and Max Eye Width 0.49 UI.

키워드

Decision Feedback Equalizer; DFE; SteongAram Latch; SR Latch; Switched capacitor; Summing; High Speed Interface; RX; CDR

제목: A 12.5-Gb/s Switched Capacitor Based Two Tap DFE With High BER Performance

저자: Cho, Yosep; Park, Jongmin; Burm, Jinwook

DOI: 10.1109/ISOCC56007.2022.10031329

발행일: 2022-10

유형: Proceedings Paper

저널명: 2022 19TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)

페이지: 304 ~ 305