A CMOS 3.2 Gb/s 4-PAM serial link transceiver

초록

A CMOS 3.2-Gb/s multilevel pulse amplitude modulation (PAM) transceiver is proposed. By using 4-PAM signaling, symbol rate is effectively decreased compared to the binary signaling. Data transmission is executed through current mode instead of voltage mode for high data transmission rate. 21 pseudo random bit sequence (PRBS) generator was designed on-chip for built-in self test (BIST) operation. The CMOS transceiver is designed in 0.18 mu m CMOS process. It achieves 3.2-Gb/s data rate, and total power consumption is 148 mW.

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